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"Radiation Damage Characterization of Digital Integrated Circuits"
S. Sondón, P. Mandolesi, P. Julián, F. Palumbo, M. Alurralde and A. Filevich
Proc. of the "10th Latin America Test Workshop" (LATW '09), Búzios, Rio de Janeiro, Brazil, March 2-5, 2009.
2009 10th Latin American Test Workshop (LATW), Volume CFP09LAT-POD, Institute of Electrical and Electronics Engineers (2009) 171-175
ISBN: 978-1-4244-4207-2 (softcover)
978-1-4244-4206-5 (cdrom)
978-1-4244-4207-2 (pod)
A set of gates and registers was fabricated on a submicron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a tandem accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.
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