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"Analysis and comparison of the CV-Dispersion of high-k, bi-layered MOS InGaAs/InP stacks"
Sebastian M. Pazos, Felix Palumbo and Fernando L. Aguirre
Proc. of the "1st Conference on PhD Research in Microelectronics and Electronics in Latin America" (PRIME-LA 2017), San Carlos de Bariloche, Argentina, February 20-23, 2017. Compiled by Alfonso Chacón and Alfredo Arnaud
2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA), Volume CFP17K02-ART, Published by the Institute of Electrical and Electronics Engineers (IEEE). (2017) 17-19
ISBN: 978-1-5090-3962-0 (hardcover)
978-1-5090-3963-0 (on-line)
978-1-5090-3962-3 (usb)
978-1-5090-3964-7 (pod)
In this work, the origin of the C-V dispersion in accumulation on High-k Bi-layered InGaAs and InP substrate MOS capacitors is discussed. Using different proportions of Al2O3 and HfO2 dielectrics on a 10nm thick gate insulator, the influence of each layer and its defects is studied. Results show that increasing the thickness of the Al2O3 interfacial layer contributes to improve the quality of the structure in terms of border trap density. InP based stacks show the same tendencies of InGaAs based stacks, but with a higher overall dispersion attributed to the quality of the dielectric deposition on different substrates.
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